1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and more particularly to a nonvolatile semiconductor memory device including memory cells formed to have double-layered gate electrodes each of which includes a floating gate electrode and control gate electrode.
2. Description of the Related Art
As an example of a nonvolatile semiconductor memory device including memory cells formed to have double-layered gate electrodes each of which includes a floating gate electrode and control gate electrode, a NAND nonvolatile semiconductor memory device is known. The memory cell array of the NAND nonvolatile semiconductor memory device is configured to have a plurality of NAND cell units CU. Each of the NAND cell units CU includes a memory cell string having a preset number of memory cells serially connected and two selection transistors connected to the drain side and source side of the memory cell string. Further, in the memory cell array, a bit line contact electrode electrically connected to the bit line and a source line contact electrode electrically connected to the source line are respectively arranged in positions adjacent to the respective selection transistors.
Each memory cell has a double-layered gate electrode which has a control gate electrode laminated above a floating gate electrode with a gate-gate insulating film disposed therebetween. Part of the control gate electrode is filled in between the floating gate electrodes which are opposed to each other in a direction (channel width direction: a direction perpendicular to the direction in which the channel current flows) along the word line configured by the control gate electrode with a gate-gate insulating film disposed therebetween and a certain coupling ratio of the memory cells can be attained.
However, for example, when the distance between the floating gate electrodes becomes smaller than twice the film thickness of the gate-gate insulating film with miniaturization of the memory cells, the space between the floating gate electrodes is filled with only the gate-gate insulating film. Then, there occurs a problem that the capacitance between the floating gate electrode and the control gate electrode becomes smaller, a sufficient coupling ratio of the memory cells cannot be attained and the characteristics of the memory cells will deteriorate.
Further, when the control gate electrode is formed of silicon, for example, the width of the control gate electrode filled in between the floating gate electrodes tends to become small even if the control gate electrode can be filled. In short, if the control gate electrode filled in between the floating gate electrodes is completely depleted at the operation time of the memory cell, there occurs a problem that the capacitance between the floating gate electrode and the control gate electrode becomes smaller, a sufficient coupling ratio of the memory cells cannot be attained and the characteristics of the memory cells will deteriorate.
A stacked-gate semiconductor memory in which a variation in the threshold voltage is suppressed by forming the cross-sectional area of the floating gate electrode in the width direction in a convex shape to reduce the capacitance between the floating gate electrodes is already proposed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2004-022819). However, according to the contents of this proposal, there occurs a problem that the step difference of the floating gate electrodes makes it difficult to etch the gate-gate insulating film filled in between the floating gate electrodes.